LPMACK=LPMACK_0, IDAM=IDAM_0, SUPV=SUPV_0, LPRIOEN=LPRIOEN_0, IRMQ=IRMQ_0, WAKSRC=WAKSRC_0, WAKMSK=WAKMSK_0, RFEN=RFEN_0, FRZ=FRZ_0, MDIS=MDIS_0, SRXDIS=SRXDIS_0, SOFTRST=SOFTRST_0, FRZACK=FRZACK_0, NOTRDY=NOTRDY_0, SLFWAK=SLFWAK_0, HALT=HALT_0, WRNEN=WRNEN_0, AEN=AEN_0
Module Configuration Register
| MAXMB | This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes |
| IDAM | This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below 0 (IDAM_0): Format A One full ID (standard or extended) per ID filter Table element. 1 (IDAM_1): Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. 2 (IDAM_2): Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. 3 (IDAM_3): Format D All frames rejected. |
| AEN | This bit is supplied for backwards compatibility reasons 0 (AEN_0): Abort disabled 1 (AEN_1): Abort enabled |
| LPRIOEN | This bit is provided for backwards compatibility reasons 0 (LPRIOEN_0): Local Priority disabled 1 (LPRIOEN_1): Local Priority enabled |
| IRMQ | This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK 0 (IRMQ_0): Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. 1 (IRMQ_1): Individual Rx masking and queue feature are enabled. |
| SRXDIS | This bit defines whether FlexCAN is allowed to receive frames transmitted by itself 0 (SRXDIS_0): Self reception enabled 1 (SRXDIS_1): Self reception disabled |
| WAKSRC | This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up 0 (WAKSRC_0): FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. 1 (WAKSRC_1): FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus |
| LPMACK | This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode 0 (LPMACK_0): FLEXCAN not in any of the low power modes 1 (LPMACK_1): FLEXCAN is either in Disable Mode, or Stop mode |
| WRNEN | When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register 0 (WRNEN_0): TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. 1 (WRNEN_1): TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. |
| SLFWAK | This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode 0 (SLFWAK_0): FLEXCAN Self Wake Up feature is disabled 1 (SLFWAK_1): FLEXCAN Self Wake Up feature is enabled |
| SUPV | This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode 0 (SUPV_0): FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses 1 (SUPV_1): FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location |
| FRZACK | This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped 0 (FRZACK_0): FLEXCAN not in Freeze Mode, prescaler running 1 (FRZACK_1): FLEXCAN in Freeze Mode, prescaler stopped |
| SOFTRST | When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers 0 (SOFTRST_0): No reset request 1 (SOFTRST_1): Reset the registers |
| WAKMSK | This bit enables the Wake Up Interrupt generation. 0 (WAKMSK_0): Wake Up Interrupt is disabled 1 (WAKMSK_1): Wake Up Interrupt is enabled |
| NOTRDY | This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode 0 (NOTRDY_0): FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode 1 (NOTRDY_1): FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode |
| HALT | Assertion of this bit puts the FLEXCAN module into Freeze Mode 0 (HALT_0): No Freeze Mode request. 1 (HALT_1): Enters Freeze Mode if the FRZ bit is asserted. |
| RFEN | This bit controls whether the Rx FIFO feature is enabled or not 0 (RFEN_0): FIFO not enabled 1 (RFEN_1): FIFO enabled |
| FRZ | The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level 0 (FRZ_0): Not enabled to enter Freeze Mode 1 (FRZ_1): Enabled to enter Freeze Mode |
| MDIS | This bit controls whether FLEXCAN is enabled or not 0 (MDIS_0): Enable the FLEXCAN module 1 (MDIS_1): Disable the FLEXCAN module |